1296000440867187505有限状态机设计.ppt

IF clkEVENT AND clk = 1 THEN case state is when sd = if x=1 then z=1;else z=0; end if; when others = z=0; end case; end if; end process; END behave; 第5章、 有限状态机设计 0/0 1/0 1/0 sa 1/0 0/0 0/0 0/0 sb sc sd x/z 1/1 RESET “1111”序列检测器仿真时序图 第5章、 有限状态机设计 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_signed.all; ENTITY stack IS --16*8 PORT ( datain : IN std_logic_vector(7 downto 0); push,pop,reset,clk : IN std_logic; stackfull : out std_logic; dataout :buffer std_logic_vector(7 downto 0)); END stack; 例 、堆栈（stack）设计 第5章、 有限状态机设计 ARCHITECTURE a OF stack IS type arraylogic is array (15 downto 0) of std_logic_vector(7 downto 0); signal data : arraylogic; --此处定义了data为一个数组16?8 signal stackflag:std_logic_vector(15 downto 0); BEGIN stackfull=stackflag(0); process(clk,reset,pop,push) variable selfunction :std_logic_vector(1 downto 0); begin selfunction:=pushpop; if reset=‘1’ then 第5章、 有限状态机设计 stackflag=(other=’0’); dataout=(other=’0’); for i in 0 to 15 loop data(i)=; end loop; elsif clk’event and clk=‘1’ then case selfunction is when 10= --push data(15)=datain; --每个8位 stackflag=1 stackflag(15 downto 1); FOR i IN 0 to 14 LOOP data(i)=data(i+1); END LOOP; 第5章、 有限状态机设计 when “01”= --pop dataout=data(15); stackflag= stackflag(14 downto 0)’0’; for i in 15 downto 1 loop data(i)=data(i-1); end loop; when others =null; end case; end if; end process; End a; 第5章