数字逻辑5章 英文课件.ppt

Chapter 5;5.1 HDL-Based Digital Design;5.1.2 HDL Tool Suites;5.1.3 HDL-Based Design Flow;5.4 The Verilog Hardware Description Language;5.4.1 Program Structure;肋蛾沦辨陕魂仔疾虫遭滚程痴己截凛舱盛镐坍拷访红阀倪字钳有柒缩昏喀数字逻辑5章 英文课件数字逻辑5章 英文课件;Note: Keywords and identifier are case sensitivity.;Syntax of a Verilog input/output declarations:;5.4.2 Logic System, Nets, Variables, and Constants;2. Nets;Syntax of Verilog wire and tri net declarations:;3. Variables;4. Constants;5.4.3 Vectors and Operators;2. Operators;5.4.4 Arrays;5.4.5 Logical Operators and Expressions;Precedence;5.4.6 Compiler Directives;5.4.7 Structural Design Elements;Verilog built-in gates:;The first format;The second format;5.4.8 Dataflow Design Elements;5.4.9 Behavioral Design Elements (Procedural Code);Procedural statements that are used within an always block:;1. Blocking and Nonblocking assignment statements;Note: Always use blocking assignments (=) in always blocks intended to create combinational logic. Always use nonblocking assignments (=) in always blocks intended to create sequential logic. Do not mix blocking and nonblocking assignments in the same always block. Do not make assignments to the same variable in two different always blocks.;2. Begin-end blocks;Ex. — Prime-number detector using multiple statements in an always block;3. If statement;4. Case statement;5. For statement;6. Repeat, while and forever statement;5.4.10 Functions and Tasks;Ex. — Verilog program for an XOR gate using an “inhibit”  function ;2. Task;5.4.11 The Time Dimension;5.4.12 Simulation;5.4.13 Test Benches;Ex. — Verilog test bench for a prime-number detector;5.4.14 Verilog Features for Sequential Logic Design;5.4.15 Synthesis