40nmCMOS工艺下的低压、低敏感性负阻负载全差分运算放大器设计.doc

  A Low-Sensitivity Negative Resistance Load Fully Differential OTA under Low Voltage 40nm CMOS Logic 5 10 Process Ning Ning, Fan Yang, Sui Zhiling, Luo Rui, Wu Shuangyi* (State Key Lab of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China. Chengdu. P. R. China. 610054) Abstract: A low-sensitivity negative resistance load fully differential operational transconductance amplifier （OTA） with low supply voltage is proposed under standard 40nm logic CMOS process. By using optimized low-sensitivity negative resistance load, the gain immunity towards process variation is effectively improved. Simulated with 40nm logic process model and 1.1V power supply, the results show that the OTA obtained a gain enhancement of 23.85dB and the gain variations is greatly limited. Key words: IC design; negative resistance load; 40nm CMOS process; low sensitivity 15 Introduction The process shrinkage is touching almost every corner of the micro-electronic world. Advancer process leads to shorter channel length, thinner gate and lower supply voltage, which means smaller chip size, faster speed and less power consumption. Benefited from this, an 20 25 30 35 expansion of portable systems, such as wireless communication devices, consumer electronics, are filling the markets. But there still exist some drawbacks under these processes, like the offsets, parasitic effects [1, 2], and the small-size effects [3], making it harder to achieve a high performance. One of the unavoidable drawbacks under standard 40nm logic process is the ultra small output resistance. In Fig.1, the output resistances of two NMOSs biased in saturated region are presented under 40/130nm standard logic processes. It can be seen that under 40nm process, the output resistance rO of the MOSFET is about one-fifth to one-sixth of that under 130nm process. This process character may bring a huge difficulty to the design of high gain amplifiers. To achieve high gain char