超低频数字频率计设计与制作毕业论文.doc

摘 要 频率检测是电子测量领域的最基本也是最重要的测量之一。频率信号抗干扰能力强、易于传输，可以获得较高的测量精度，所以测频率方法的研究越来越受到重视。本课题的等精度数字频率计设计，采用当今电子设计领域流行的EDA技术，以CPLD为核心，配合AT89C51单片机，采用多周期同步测频原理，实现了0. 1Hz-50MHz信号频率的等精度频率测量，此外，该系统还可以测方波信号宽度及高、低电平的占空比。设计中用一块复杂可编程逻辑器件CPLD(Complex Programmable Logic Device)芯片EPM7128SLC84-15完成各种时序逻辑控制、计数功能。在Quartus II平台上，用VHDL语言编程完成了CPLD的软件设计、编译、调试、仿真和下载。用AT89C51单片机作为系统的主控部件，实现整个电路的测试信号控制、数据运算处理、键盘扫描和控制数码管的显示输出。系统将单片机AT89C51的控制灵活性及CPLD芯片的现场可编程性相结合，不但大大缩短了开发研制周期，而且使本系统具有结构紧凑、体积小，可靠性高，测频范围宽、精度高等优点。采用常规数字电路设计数字频率计，所用的器件较多、连线比较复杂，而且存在延时较大、测量误差较大、可靠恻氏的缺点。采用复杂可编程逻辑器件，以EDA工具为开发手段、运用VHDL语言编程进行数字频率计的设计，将在使系统大大简化的同时，提高仪器整体的性能和可靠性。本文介绍的用FPGA实现的数字频率计，采用VHDL语言编程，用Maxplus II集成开发环境进行波形仿真、编译，并下载到FPGA中。经测试，该系统性能可靠、测量精确,详细论述了系统自上而下的设计方法及各部分硬件电路组成及单片机、CPLD的软件编程设计。使用以GW48-CK EDA实验开发系统为主的实验环境下进行了仿真和硬件验证，达到了较高的测量精度和测量速度。 关键词: 超低频;数字频率计;设计;;制作; Abstract Frequency detection is the most basic electronic measurement is one of the most important measurement. Frequency signal interference capability, easy to transport, access to high accuracy, so the frequency method of measuring more and more attention. The issue of equal precision digital frequency meter design, the use of todays popular electronic design EDA technology to CPLD as its core, with AT89C51 microcontroller, a multi-period synchronous frequency principle, to achieve the 0. 1Hz-50MHz frequency of Equal Frequency measurement, in addition, the system can also measure the width of the square wave signal and the high, low duty cycle. Design using a complex programmable logic device CPLD (Complex Programmable Logic Device) chip EPM7128SLC84-15 to complete a variety of temporal logic control, counting function. In the Quartus II platform, complete with VHDL, CPLD programming software design, coding, debugging, simulation, and download. With AT89C51 microcontroller as the main control system components, to achieve the test signal control circuit, data processing operations, the keyboard scanning and control of digital control of display output. AT89C51 the mo