24G射频低噪声放大器毕业设计.doc

摘 要 近年来，以电池作为电源的电子产品得到广泛使用，迫切要求采用低电压的模拟电路来降低功耗，所以低电压、低功耗模拟电路设计技术正成为研究的热点。本文主要讨论电感负反馈cascode-CMOS-LNA（共源共栅低噪声放大器）的噪声优化技术，同时也分析了噪声和输入同时匹配的SNIM技术。以噪声参数方程为基础，列出了简单易懂的设计原理。为了实现低电压、低噪声、高线性度的设计指标，在本文中使用了三种设计技术。第一，本文以大量的篇幅推导出了一个理想化的噪声结论，并使用Matlab分析了基于功耗限制的噪声系数，取得最优化的晶体管尺寸。第二，为了实现低电压设计，引用了一个折叠式的共源共栅结构低噪声放大器。第三，通过线性度的理论分析并结合实验仿真的方法，得出了设计一个高线性度的最后方案。另外，为了改善射频集成电路的器件参数选择的灵活性，在第四章中使用了一种差分结构。所设计的电路用CHARTER公司 0.25μm CMOS 工艺技术实现，并使用Cadence的spectre RF 工具进行仿真分析。本文使用的差分电路结构只进行了电路级的仿真，而折叠式的共源共栅电路进行了电路级的仿真、版图设计、版图参数提取、电路版图一致性检查和后模拟，完成了整个低噪声放大器的设计流程。 折叠式低噪声放大器的仿真结果为：噪声系数NF为1.30dB，反射参数S11、S12、S22分别为 -21.73dB、-30.62dB、-23.45dB，正向增益S21为 14.27dB，1dB压缩点为-12.8dBm，三阶交调点IIP3 为0.58dBm。整个电路工作在1V电源下，消耗的电流为8.19mA，总的功耗为8.19mW。所有仿真的技术指标达到设计要求。 关键字：低噪声放大器；噪声系数；低电压、低功耗；共源共栅；噪声匹配 ABSTRACT In recent years, electronics with battery supply are widely used, which cries for adopting low voltage analog circuits to reduce power consumption, so low voltage, low power analog circuit design techniques are becoming research hotspot. This paper mainly discusses noise figure optimization techniques for inductively degenerated cascode CMOS low-noise amplifiers (LNAs) with on-chip inductors. And it reviews and analyzes simultaneous noise and input matching techniques (SNIM). Based on the noise parameter equations, this paper provides clear understanding of the design principle. In order to achieve low-voltage, low noise, high-linearity of the design specifications, in this paper by three design technology. Firstly, using Matlab tool analyzes noise figure based on power-constrained, and obtain the optimum transistor size. Secondly, design a folded-cascode-type LNA to reduce the power supper. Third, through theoretical analysis of Linear and combine simulation methods, I obtain a final design of a high-linearity. On the other side, in order to improve the radio frequency integrated circuit device parameters of flexibility, this paper presents a difference in the structure in the fourth chapter. The proposed circuit de