基于FPGA的数字钟设计.doc

摘 要 伴随着集成电路技术的发展, 电子设计自动化(EDA)技术逐渐成为数字电路设计的重要手段。 基于FPGA的EDA技术的发展和应用领域的扩大与深入，使得EDA技术在电子信息，通信，自动控制，计算机等领域的重要性日益突出。 本设计给出了一种基于FPGA的多功能数字钟方法，采用EDA作为开发工具，VHDL语言和图形输入为硬件描述语言，QuartusII作为运行程序的平台，编写的程序经过调试运行，波形仿真验证，下载到EDA实验箱的FPGA芯片，实现了设计目标。 系统主芯片采用CycloneII系列EP2C35F672C8。采用自顶向下的设计思想，将系统分为五个模块:分频模块、计时模块、报时模块、显示模块、顶层模块。用VHDL语言实现各个功能模块, 图形输入法生成顶层模块. 最后用QuartusII软件进行功能仿真, 验证数字钟设计的正确性。 测试结果表明本设计实现了一个多功能的数字钟功能，具有时、分、秒计时显示功能，以24小时循环计时；具有校正小时和分钟的功能；以及清零，整点报时功能。 关键词：EDA技术；FPGA；数字钟；VHDL语言；自顶向下 Abstract Accompanied by the development of integrated circuit technology, electronic design automation (EDA) technology is becoming an important means of digital circuit design. FPGA EDA technology development and expansion of application fields and in-depth, the importance of EDA technology in the field of electronic information, communication, automatic control, computer, etc. have become increasingly prominent. This design gives a FPGA-based multifunctional digital clock using EDA as a development tool, VHDL language and graphical input hardware description language, the QuartusII as a platform for running the program, written procedures debugging and running, the waveform simulation downloaded to the FPGA chip to achieve the design goals. The main system chip CycloneII series EP2C35F672C8. Adopted a topdwn design ideas, the system is divided into five modules: frequency module, timing module, timer module, display module, the top-level module. With VHDL various functional modules, graphical input method to generate the top-level module. Last QuartusII under simulation, to verify the correctness of the digital clock design. The test results show that the design of a multifunctional digital clock, with seconds time display, 24-hour cycle timing; has a school, cleared, and the whole point timekeeping functions. Key words: EDA technology; FPGA; VHDL language; top-down; digital clock