基于FPGA的异步FIFO设计(毕业设计论文).doc

江苏科技大学 本 科 毕 业 设 计（论文） 学 院 专 业 学生姓名 班级学号 指导教师 二零壹叁年六月 江苏科技大学本科毕业论文 基于FPGA的异步FIFO设计 Asynchronous FIFO design based on FPGA 摘 要 在现代集成电路芯片中，随着设计规模的不断扩大，一个系统往往包含多个时钟，如何进行异步时钟间的数据传输成为了一个很重要的问题。异步FIFO（First In First Out）是一种先进先出电路，可以在两个不同的时钟系统间进行快速准确的数据传输，是解决异步时钟数据传输问题的简单有效的方案。异步FIFO在网络接口、数据采集和图像处理等方面得到了十分广泛的应用，由于国内对该方面研究起步较晚，国内的一些研究所和厂商开发的FIFO电路还远不能满足市场和军事需求。 由于在异步电路中，时钟间的周期和相位完全独立，以及亚稳态问题的存在，数据传输时的丢失率不为零，如何实现异步信号同步化和降低亚稳态概率以及正确判断FIFO的储存状态成为了设计异步FIFO电路的难点。本课题介绍了一种基于FPGA的异步FIFO 电路设计方法。课题选用Quartus II软件，在Cyclone II系列的EP2C5T144C8N芯片的基础上，利用VHDL 硬件描述语言进行逻辑描述，采用层次化、描述语言和图形输入相结合的方法设计了一个RAM深度为128 bit，数据宽度为8 bit的高速、高可靠的异步FIFO电路，并对该电路功能进行时序仿真测试和硬件仿真测试。 关键词：异步FIFO；同步化；亚稳态；仿真测试 Abstract In modern IC chips, with the continuous expansion of the scale of design, a system always contains several clocks. How to transmit data between the asynchronous clocks become a very important problem.Asynchronous FIFO (First In First Out) is a first-in, first-out circuit, it can transmit data between two diffent clock systems fastly and accurately, it is also a simple and effective solution to solve the problem of asynchronous clock data transfer. The asynchronous FIFO has a very wide range of applications in network interface, data acquisition and image processing.But because of the aspect of a late start, some domestic research institutes and manufacturers which research the FIFO circuit also can not meet the needs of the market and the military. In the asynchronous circuit, because of that the clock cycle and phase is completely independent, and the presence of metastability problems, the loss rate of data transmission is not zero. How to implement asynchronous signal synchronization, reduce the probability of metastability and judge the state of the FIFO storage correc