低功耗论文：深亚微米SoC芯片的低功耗物理设计.docVIP

低功耗论文：深亚微米SoC芯片的低功耗物理设计 【中文摘要】时序、面积和功耗是芯片设计中的重要因素,随着半导体工艺的进步,功耗因素在芯片设计中的关注度逐渐增高。业界已经有一套低功耗设计方法,我们在一款低功耗芯片的设计实现以及验证流程中,使用了基于IEEE 1801标准Unified Power Format (UPF)的部分技术,成功的完成了从RTL到GDSII的全部讨程,芯片已经完成投片并进行了测试,测试表明芯片一切正常工作,从而验证了所用到的低功耗设计方法的可行性。本文先介绍了物理设计中的低功耗技术,描述了CMOS电路功耗的组成,包括动态功耗与静态功耗以及它们之间的矛盾。介绍了门控时钟、多阈值电压逻辑、多供电电压和门控电源等低功耗设计的技术。分析了多电压供电的策略和设计中遇到的困难,对常用的电平转换单元进行了描述。电源门控技术是比较复杂的一种低功耗设计方法,其中还用到了许多特殊的电源管理器件,如MTCMOS、隔离单元、保持寄存器等,而且电源开关网络的控制和门控电源控制器的设计都要经过深入的研究。本文介绍了Synopsys基于UPF的低功耗设计流程,对UPF文件的内容进行详细的分析。UPF描述了设计的功耗意图,如芯片电源管理的供电网络,隔离单元、电平转换单元的插入,电源开关单元等各个方面。它指定如何为各个设计建立电源网络,各个电源线之间的行为,以及用来支持设计动态电源关断额外的逻辑功能等。UPF并不提供布局布线的信息,和RTL描述设计也是分开的。UPF文件主要的内容包括：对电压域的描述,对电源网络的描述,对电源关断单元的描述,对隔离单元的描述,对电平转换单元的描述,对电源状态的描述。最后利用Synopsys的EDA平台对SEP6010B芯片进行低功耗物理设计,包括布图规划,电压域的创建,电源关断单元的插入、布局以及控制信号的连接,电源网络综合和分析,布局,时钟树综合,布线。 【英文摘要】Timing, area and power are important factors in chip design. Along with advances in semiconductor technology, the attention of power factor in chip design gradually increased. Industry has a set of low-power design methods. Recently, we designed a chip with low power implementation and verification. We used part of IEEE1801 standard based Unified Power Format (UPF) technology, successfully completed the whole flow of RTL to GDSII. The chip has been manufactured and tested, the low-power design methods of this chip has been verified.This paper first introduces the low power technology of physical design. We describe the theory of power in CMOS circuits, includes dynamic power and static power, and the relation of dynamic power and static power. Clock gating, multiple threshold voltage logic, multi-VDD and power gating technology was introduced. The strategy and difficult of multi-VDD was analyzed. Power gating is a complicated low power design technology. There are some special PM cells, such as MTCMOS, isolation cell, retention registers. The power switch network and power gating controller should be carefully researched.Synopsys UPF low power design flow was introduced, an