【精品】课件---编译器参数调优方法.ppt

General Optimizations /Od, -O0: disable optimizations /Zi, -g: Create Symbols /O1, -O1: Optimizes for speed without increasing code size – i.e. disables library function inlining /O2, -O2 – default – Optimize for speed /O3, -O3 – High-level optimizations Instruction Scheduling Schedule instructions to be optimal for specific processor instruction latencies and cache sizes Shift/Multiply Latency Pentium Shift has ~1x latency of adds Multiply has ~10x latency of adds Pentium Pro, II, and III Shift has ~1x latency of adds Multiply has ~3x latency of adds Pentium 4 (may change in future releases) Shift has ~8x latency of adds Multiply has ~26x latency of adds for (int i=0;ilength;i++) { p[i] = q[i] * 32; } .B1.7: # -tpp6 movl (%ebx,%edx,4),%eax shll $5, %eax movl %eax, (%esi,%edx,4) incl %edx cmpl %ecx, %edx jl .B1.7 .B1.7: # -tpp7 movl (%ebx,%edx,4),%eax addl %eax, %eax addl %eax, %eax addl %eax, %eax addl %eax, %eax addl %eax, %eax movl %eax, (%esi,%edx,4) addl $1, %edx cmpl %ecx, %edx jl .B1.7 Which Processor: [a]x? Automatic Processor Dispatch Single executable Pentium 4 target that runs on all x86 processors. For Target Processor it uses: Processor Specific Opcodes Prefetch (Pentium III only) Vectorization Low Overhead Some increase in code size Can mix and match: -xK –axW together makes Xeon/Pentium 4 the target and Pentium III the default Vectorization Automatically converts loops to utilize MMX/SSE/SSE2 instructions and registers. Data types: char/short/int/float/double (but not mixed) Can Use Short Vector Math Library Enabled through -[Q]xW, -[Q]xK, -[Q]axW, -[Q]axK -vec_report3 tells you which loops were vectorized, and if not, why not. High Level Optimizer Windows: /O3 or Linux: -O3 Use with –xW, -xK, -QxW, -QxK, etc. additional loop optimizat