UART驱动.docVIP

一个好用的串口UART程序 ========================================================================== //-----------------------------------------------------// Design Name : uart // File Name?? : uart.v// Function??? : Simple UART// Coder?????? : Deepak Kumar Tala//-----------------------------------------------------module uart (reset????????? , txclk????????? , ld_tx_data???? ,//tx_data??????? ,tx_enable????? ,// tx_out???????? ,tx_empty?????? ,rxclk????????? ,uld_rx_data??? ,rx_data??????? ,rx_enable????? ,rx_in????????? ,rx_empty);// Port declarationsinput??????? reset????????? ;input??????? txclk????????? ;input??????? ld_tx_data???? ;input [7:0] tx_data??????? ;input??????? tx_enable????? ; output?????? tx_out???????? ;output?????? tx_empty?????? ;input??????? rxclk????????? ;input??????? uld_rx_data??? ;output [7:0] rx_data??????? ;input??????? rx_enable????? ;input??????? rx_in????????? ;output?????? rx_empty?????? ; // Internal Variables reg [7:0]??? tx_reg???????? ;reg????????? tx_empty?????? ;reg????????? tx_over_run??? ;reg [3:0]??? tx_cnt???????? ;reg????????? tx_out???????? ;reg [7:0]??? rx_reg???????? ;reg [7:0]??? rx_data??????? ;reg [3:0]??? rx_sample_cnt ;reg [3:0]??? rx_cnt???????? ; reg????????? rx_frame_err?? ;reg????????? rx_over_run??? ;reg????????? rx_empty?????? ;reg????????? rx_d1????????? ;reg????????? rx_d2????????? ;reg????????? rx_busy??????? ; // UART RX Logicalways @ (posedge rxclk or posedge reset)if (reset) beginrx_reg??????? = 0; rx_data?????? = 0;rx_sample_cnt = 0;rx_cnt??????? = 0;rx_frame_err = 0;rx_over_run?? = 0;rx_empty????? = 1;rx_d1???????? = 1;rx_d2???????? = 1;rx_busy?????? = 0;end else begin// Synchronize the asynch signalrx_d1 = rx_in;rx_d2 = rx_d1;// Uload the rx dataif (uld_rx_data) begin??? rx_data = rx_reg;??? rx_empty = 1;end// Receive data only when rx is enabledif (rx_enable) begin??? // Check if just received start of frame??? if (!rx_busy !rx_d2) begi