SRIO网络的设计与应用.ppt

* 7.3 C6678 DirectIO数据传输 Load/Store 寄存器2 7.3 C6678 DirectIO数据传输 C6678 DirectIO的特点 SrcID_MAP选用16个RIO_DEVICEID_REGn的内容作为SOURCE ID，针对多核应用； C6678的LSU一次最多可发送1MB，效率高（C6455为4KB） C6678具有32组shadow register，每个LSU可对应若干组shadow register，可同时启动多组传输设置； 具有具有LCB和LTID，可区别对同一LSU不同shadow register的操作及其返回结果； 当传输不成功的时候，具有RESTART和Flush的功能。 7.3 Doorbell中断的实现 初始化Doorbell中断 与一般的中断初始化基本相同 有8个INTDST，分别为0~7,它们可选择的中断事件为20,21和22,通过INTMUX选择具体的中断号 需要额外设置的寄存器： DOORBELL0_ICCR：Interrupt Condition Clear Register DOORBELL0_ICRR：Interrupt Condition Routing Registers INTDST0_RATE_CNTL:Interrupt Rate Control Register 7.3 Doorbell中断的实现 发送Doorbell中断 在LSU_reg5中设定Packettype 0xA0； 在LSU_reg5的Drbll Info中添加信息； Doorbell中断服务子程序 与普通中断服务子程序相同 通过DOORBELL0_ICCR清除中断标志 通过设置INTDSTn_RATE_CNTL以便及时响应下一个中断 8 基于SRIO互联的系统实例 SAR-GMTI处理机 8 基于SRIO互联的系统实例 ISAR实时成像处理机 8 基于SRIO互联的系统实例 图像处理子系统—实物照片 8 基于SRIO互联的系统实例 图像处理子系统—原理框图 * * The RapidIO Gen 2 ecosystem has grown to encompass many DSP, FPGA, NPU, and processor vendors. * * * * * * * * * * * * * * * * * The interrupt conditions are programmable to select the interrupt output that will be driven. Each condition is independently programmable to use any of the interrupt destinations supported by the device. For example, a quad core device may support four CPU servicing interrupt destinations, one per core INTDST0 for Core0, INTDST1 for Core1, INTDST2 for Core2, and INTDST3 for Core3 . In addition, INTDST4 may be globally routed to all cores and provide notification of a change in the Error Status interrupt ICSR. INTDST5 may be globally routed to all cores and provide notification of a change in the Device Reset interrupt ICSR. The routing defaults are shown below. When the rate control counter register is written, and the counter value reaches zero note that the CPU may write zero immediately for a zero count , the interrupt pulse generation logic is allowed to fire a single pulse if any bits in the corresponding ICSR register bits are set * * SAR/GMTI实时信号处理系统是采用FPGA和DSP异构并行处