DE2平台上EP2C35F672的引脚分配表.doc

附件A DE2平台上EP2C35F672的引脚分配表 Signal Name FPGA Pin No. Description SW SW[0] PIN_N25 Toggle Switch[0] SW[1] PIN_N26 Toggle Switch[1] SW[2] PIN_P25 Toggle Switch[2] SW[3] PIN_AE14 Toggle Switch[3] SW[4] PIN_AF14 Toggle Switch[4] SW[5] PIN_AD13 Toggle Switch[5] SW[6] PIN_AC13 Toggle Switch[6] SW[7] PIN_C13 Toggle Switch[7] SW[8] PIN_B13 Toggle Switch[8] SW[9] PIN_A13 Toggle Switch[9] SW[10] PIN_N1 Toggle Switch[10] SW[11] PIN_P1 Toggle Switch[11] SW[12] PIN_P2 Toggle Switch[12] SW[13] PIN_T7 Toggle Switch[13] SW[14] PIN_U3 Toggle Switch[14] SW[15] PIN_U4 Toggle Switch[15] SW[16] PIN_V1 Toggle Switch[16] SW[17] PIN_V2 Toggle Switch[17] DRAM DRAM_ADDR[0] PIN_T6 SDRAM Address[0] DRAM_ADDR[1] PIN_V4 SDRAM Address[1] DRAM_ADDR[2] PIN_V3 SDRAM Address[2] DRAM_ADDR[3] PIN_W2 SDRAM Address[3] DRAM_ADDR[4] PIN_W1 SDRAM Address[4] DRAM_ADDR[5] PIN_U6 SDRAM Address[5] DRAM_ADDR[6] PIN_U7 SDRAM Address[6] DRAM_ADDR[7] PIN_U5 SDRAM Address[7] DRAM_ADDR[8] PIN_W4 SDRAM Address[8] DRAM_ADDR[9] PIN_W3 SDRAM Address[9] DRAM_ADDR[10] PIN_Y1 SDRAM Address[10] DRAM_ADDR[11] PIN_V5 SDRAM Address[11] DRAM_DQ[0] PIN_V6 SDRAM Data[0] DRAM_DQ[1] PIN_AA2 SDRAM Data[1] DRAM_DQ[2] PIN_AA1 SDRAM Data[2] DRAM_DQ[3] PIN_Y3 SDRAM Data[3] DRAM_DQ[4] PIN_Y4 SDRAM Data[4] DRAM_DQ[5] PIN_R8 SDRAM Data[5] DRAM_DQ[6] PIN_T8 SDRAM Data[6] DRAM_DQ[7] PIN_V7 SDRAM Data[7] DRAM_DQ[8] PIN_W6 SDRAM Data[8] DRAM_DQ[9] PIN_AB2 SDRAM Data[9] DRAM_DQ[10] PIN_AB1 SDRAM Data[10] DRAM_DQ[11] PIN_AA4 SDRAM Data[11] DRAM_DQ[12] PIN_AA3 SDRAM Data[12] DRAM_DQ[13] PIN_AC2 SDRAM Data[13] DRAM_DQ[14] PIN_AC1 SDRAM Data[14] DRAM_DQ[15] PIN_AA5 SDRAM Data[15] DRAM_BA_0 PIN_AE2 SDRAM Bank Address[0] DRAM_BA_1 PIN_AE3 SDRAM Bank Address[1] DRAM_LDQM PIN_AD2 SDRAM Low-byte Data Mask DRAM_UDQM PIN_Y5 SDRAM High-byte Data Mask DRAM