基于FPGA的数字锁相环设计.pdfVIP

2011 2 35 FPGA 1 2 1 高 亮 , 肖鹏程 , 张荣福 ( 1. 上海理工大学 光电信息与计算机工程学院, 上海 200093; 2. 复旦大学, 上海 201203) : 简要介绍异或 数字锁相环的工作原理和组成部分, 并且分析了各模块参数选择对数字锁相环纹波的影响文章针对 于此, 设计出一种最佳匹配参数下的数字锁相环, 在 FPGA 平台上用 Verilog HDL语言实现硬件电路, 整 个系统具有快速锁定, 纹波 最小以及精度高等优点 : 数字锁相环; FPGA; Verilog HDL : TN 92 : A : 1006- 239 ( 2011) 02- 0035- 0 Design of D igital Phase Locked L oop Based on FPGA 1 2 1 GAO L iang , XIAO Pengcheng , ZHANG Rongfu ( 1. School of Opticalelectrical and Compu ter Engineering, Un ivers ity of Shanghai for Science and Technology, Shanghai 200093, Ch ina; 2. Fudan University, Shanghai 201203, China) Abs tract: The composing and principle of XORD igital Phase Locked Loop are smi p ly described. And every modules param eters based on the ripple of DPLL are analyzed. A DPLL w ith best parameters m atch is introduced, w hich is ach ievedw ith Verilog language on FPGA platform. The quality of system appears quick latching, m in mi um rip ple and h igh precision. K ey w ord s: DPLL; FPGA; Verilog HDL 1. 1 1 ( EXOR) 1, F out F in, ( DCO) , (), F = out gap in , - , K , out , F out 50%, , , , 1. 2 0, ; DCO , DCO D