Capacitive SAR ADC Input Offset Reduction by Stray Capacitance Compensation.pdfVIP

Proceedings of the 7th International Caribbean Conference on Devices, Circuits and Systems, Mexico, Apr. 28-30, 2008 Capacitive-SAR ADC Input Offset Reduction by Stray Capacitance Compensation Vilson R. Mognon, Carlos A. dos Reis Filho School of Electrical and Computer Engineering State University of Campinas-UNICAMP Campinas – SP, Brazil {mognon, carlos_reis}@lpm.fee.unicamp.br Abstract - A 10-bit, 80-kS/s charge-redistribution successive with nearby conductive layers and with the ground substrate. approximation analog-to-digital converter is presented, which As these stray capacitances can compete with the intentional incorporates a novel stray capacitance compensation technique capacitances for the role of quantizing charges, they can that is appropriate for low-power design in order to produce huge offset voltage errors and even distortion in a accomplish input voltage offset reduction. Three different non-meticulous layout. In switched-capacitor circuits, the versions of the ADC were fabricated in 0.35mmm, 4M2P mm effects of stray capacitances can be largely reduced by using standard CMOS process. The compensation mechanism stray insensitive circuit topologies, most of which are based implemented in one of the ADC versions proved its on preserving the switchable terminals of every capacitor at effectiveness by showing an input