中山大学软件学院专业课计算机组成原理课件第4章.pptVIP

Control Unit Micro-Operations Micro-Operations Constituent Elements of Program Execution Fetch - 4 Registers Memory Address Register (MAR) Connected to address bus Specifies address for read or write op Memory Buffer Register (MBR) Connected to data bus Holds data to write or last data read Program Counter (PC) Holds address of next instruction to be fetched Instruction Register (IR) Holds last instruction fetched Fetch Sequence Address of next instruction is in PC Address (MAR) is placed on address bus Control unit issues READ command Result (data from memory) appears on data bus Data from data bus copied into MBR PC incremented by 1 (in parallel with data fetch from memory) Data (instruction) moved from MBR to IR MBR is now free for further data fetches Rules for Clock Cycle Grouping Proper sequence must be followed MAR - (PC) must precede MBR - (memory) Conflicts must be avoided Must not read write same register at same time MBR - (memory) IR - (MBR) must not be in same cycle Also: PC - (PC) +1 involves addition Use ALU May need additional micro-operations Interrupt Cycle Instruction Cycle Flowchart for Instruction Cycle Functional Requirements Basic Elements of Processor Types of Micro-operation Transfer data between registers Transfer data from register to external Transfer data from external to register Perform arithmetic or logical ops Functions of Control Unit More explicitly, the control unit performs two basic task: sequencing and execution Sequencing Causing the CPU to step through a series of micro-operations Execution Causing the performance of each micro-op This is done using Control Signals Control Signals Control Signals- Inputs Clock One micro-instruction (or set of parallel micro-instructions) per clock cycle Instruction register Op-code for current instruction Determines which micro-instructions are performed Flags State of CPU Results of previous operations From control bus Interrupts Acknowledgements Control Signals - output Within CPU Ca