Chapter 12CPU Structure and Function.ppt

Chapter 12CPU Structure and Function CPU Sequence Fetch instructions Interpret instructions Fetch data Process data Write data CPU With Systems Bus CPU Internal Structure Registers CPU must have some working space (temporary or scratch pad storage) Top level of memory hierarchy Number and function vary between processor designs User Visible Registers General Purpose Data Address Control General Purpose Registers May be true general purpose May be used for data or addressing May be restricted Data May include Accumulator Addressing May include Segment Register(s) General Purpose Registers Design Decision Make them general purpose ? Increase flexibility and programmer options Increase instruction size complexity Make them specialized Smaller (faster) instructions Less flexibility How Many GP Registers? Between 8 – 32 ? Fewer = more memory references More does not tend to reduce memory references and takes up processor real estate How big? Large enough to hold full address Large enough to hold full word - Sometimes possible to combine two data registers Control Status Registers Program Counter Instruction Decoding Register Memory Address Register Memory Buffer Register Program Status Word Control - Condition Code Registers CC: Sets of individual bits e.g. result of last operation was zero Can be read (implicitly) by programs e.g. Jump if zero Usually can not be set by programs Program Status Word A set of status and/or control bits Includes Condition Codes Priority, Interrupt enable/disable Supervisor State information - Kernel Mode - Not available to user programs (Used by operating system) (Allows privileged instructions to execute) Other Registers May have registers pointing to: Process control blocks Interrupt Vectors Note: CPU design and operating system design are closely linked Example Register Organizations Instruction Cycle with Indirect Data Flow (Fetch Diagram) Data Flow (I