03_QuartusII时序优化策略.ppt

Quartus II Software Design Series : Optimization Optimization Techniques – Timing Optimization Timing Optimization General Recommendations Analyzing Timing Failures Solving Typical Timing Failures General Recommendations Clocks I/O Asynchronous Control Signals Many of these suggestions are found in Timing Optimization Advisor Quartus II Handbook Clocks Optimize for Speed Apply globally Apply hierarchically Apply to specific clock domain Enable netlist optimizations Enable physical synthesis Global Speed Optimization Select speed Default is balanced Area-optimized designs may also show speed improvements May result in increased logic resource usage Individual Optimization Optimization Technique logic option Use Assignment Editor or Tcl to apply to hierarchical block Speed Optimization Technique for Clock Domains logic option Use Assignment Editor or Tcl to apply to clock domain or between clock domains Synthesis Netlist Optimizations Further optimize netlists during synthesis Types WYSIWYG primitive resynthesis Gate-level register retiming Physical Synthesis Re-synthesis based on fitter output Makes incremental changes that improve results for a given placement Compensates for routing delays from fitter Physical Synthesis Types Targeting performance: Combinational logic Asynchronous signal pipelining Register duplication Register retiming Targeting fitting Physical synthesis for combinatorial logic Logic to memory mapping Effort Trades performance vs. compile time Normal, extra or fast New or modified nodes appear in Compilation Report Combinational Logic Swaps look-up table (LUT) ports within LEs to reduce critical path LEs Asynchronous Control Signals Improve Recovery Removal Timing Make control signal non-global Project-wide Assignments ? Settings ? Fitter Settings ? More Settings Individually Set Global Signal logic option to Off Enable “Automatic asynchronous signal pipelining” option (physical synthesis) Asynchronous Signal Pipelining Adds pipe