CMOS单片集成超低压差线性稳压器设计.pdf

第30卷第3期 电子器件 v01．30No．3 0f J伽mlEIect啪DE晰ce5 2007年6月cIlineSe Jun．2007 ofaCMoSMonolithicVLDo Design VoltageRegulator。 ⅢH“以1”，ZoUX“P—c庇Pn91 ＼2．’％^n聍，”s￡打“￡P ， o厂mip6“izi村g丁_f矗竹o￡og了Vn小d打430050 CMOSmonolithiclow Abstract：This amonolithic paperpresented very dropout Thestructureand withfunctionsofthermal current andfasttransient． protection，intemallimiting princi— ofthe were were andsub—blockcircuitswere methodsandissues ples analyzed given．Design chip V simulationresults too．The hasawide of from2．5 to6V． The regulator rangepowersupply Hspice showthatthe is0．4 mAand52 mA the typicaldropoutmV@1 mV@150respectively，andtypicalvoltage errorwas line errorwas Inaddition，the10ad 0．OOO12％and regulation O．0126％／V． typicalregulation the currentislessthan typicalquiescent 85肚A． low line Keywords：verydropout(VI。DO)；voltageregulator；voltageregulation；loadregulation；10wquies— CentCUrrent EEACC：2570D CMoS单片集成超低压差线性稳压器设计* 余 华L2，邹雪城 ，1．华中科技大学电子与科学技术系，武汉430074、 ＼2．武汉船舶职业技术学院，武汉430050