外文翻译--数字信号处理器重新采纳多核架构.doc

/ Digital Signal Processing Chips reembrace multicore architecture Posted: 03 Nov 2008 Adding cores to a processor to gain a performance boost, while lowering power demand, has become standard practice in the computing and embedded processor industries. While a similar evolution seems inevitable for all types of high-performance processing, prior experience has made DSP vendors more selective in applying the multicore approach. DSPs are now beginning to reembrace multicore architectures, but mainly for specific applications possessing well-partitioned processing tasks. Perform partitioning A DSP application often comprises only a few highly complex tasks, and system performance improvements depend on hastening task execution, not simply running more tasks. Instead of partitioning at the task level, this system often requires partitioning at the algorithm level. The overall task, such as compressing a video stream, must be broken into steps that can run in parallel on separate cores. The task scheduler or OS cannot perform such partitioning; it must come during the software design. Many DSP application developers avoid the multicore approach because of the difficulty of algorithm partitioning. At the same time, some tasks such as encryption are not suitable to parallelization. Homogenous vs. heterogeneous This doesnt mean that the multicore approach hasnt been tried with DSPs. PicoChip has long had its picoArray architecture that puts multiple, identical cores together for high-performance DSP. In most cases, however, multicore design offerings with DSP had not been homogeneous—having multiple copies of the same core. Instead, they integrated a DSP core with a RISC CPU core. Such heterogeneous DSPs, for instance, have been part of multicore processor designs for a number of years in the handsets and communications industries. The applications these processors targeted readily separate into signal processing tasks for the DSP and control tasks for the RISC CPU,