(江帆 丁康一 侯宝义)数字逻辑课程设计.docVIP

姓名和学号 江帆 2010042020009 丁康一 2010042020003 侯宝义 2010042010003 选择设计一，设计三，设计五 设计一 七段显示译码器设计；要求对未用编码1010~1111进行讨论 我从最小成本考虑，所以为了简化电路，对10到15的未用编码设为d， 真值表为 EN D C B A SEG A SEG B SEG C SEG D SEG E SEG F SEG G 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 1 1 0 1 0 0 0 1 0 1 1 0 0 0 0 1 0 0 1 0 1 1 0 1 1 0 1 1 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 0 0 0 0 1 1 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 0 1 1 1 1010~1111 d d d d d d d 由上述的真值表可以得到表达式为 有上述的表达式在quartus 中连接电路如下 仿真得到的波形是 然后用软件生成的对应的Verilog程序如下 // Copyright (C) 1991-2008 Altera Corporation // Your use of Altera Corporations design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // PROGRAM Quartus II // VERSION Version 8.1 Build 163 10/28/2008 SJ Full Version // CREATED ON Sat Jun 09 17:14:12 2012 module \11 ( A, B, C, D, SA, SB, SC, SD, SE, SF, SG ); input A; input B; input C; input D; output SA; output SB; output SC; output SD; output SE; output SF; output SG; wire gdfx_temp0; wire SYNTHESIZED_WIRE_0; wire SYNTHESIZED_WIRE_1; wire SYNTHESIZED_WIRE_2; wire SYNTHESIZED_WIRE_35; wire SYNTHESIZED_WIRE_4; wire SYNTHESIZED_WIRE_36; wire SYNTHESIZED_WIRE_37; wire SYNTHESIZED_WIRE_12; wire SYNTHESIZED_WIRE_13; wire SYNTHESIZED_WIRE_14; wire SYN