verilog例程.pptVIP

verilog例程 例1 4 位全加器 module adder4(cout,sum,ina,inb,cin); output[3:0] sum; output cout; input[3:0] ina,inb; input cin; assign {cout,sum}=ina+inb+cin; endmodule 【例2】4 位计数器 module count4(out,reset,clk); output[3:0] out; input reset,clk; reg[3:0] out; always @(posedge clk) begin if (reset) out=0; //同步复位 else out=out+1; //计数 end endmodule 【例3】用case 语句描述的4 选1 数据选择器 module mux4_1(out,in0,in1,in2,in3,sel); output out; input in0,in1,in2,in3; input[1:0] sel; reg out; always @(in0 or in1 or in2 or in3 or sel) //敏感信号列表 case(sel) 2b00: out=in0; 2b01: out=in1; 2b10: out=in2; 2b11: out=in3; default: out=2bx; endcase endmodule 例4 同步置数、同步清零的计数器 module count(out,data,load,reset,clk); output[7:0] out; input[7:0] data; input load,clk,reset; reg[7:0] out; always @(posedge clk) //clk 上升沿触发 begin if (!reset) out = 8h00; //同步清0，低电平有效 else if (load) out = data; //同步预置 else out = out + 1; //计数 end endmodule 例6 用always 过程语句描述的简单算术逻辑单元 `define add 3d0 `define minus 3d1 `define band 3d2 `define bor 3d3 `define bnot 3d4 module alu(out,opcode,a,b); output[7:0] out; reg[7:0] out; input[2:0] opcode; //操作码 input[7:0] a,b; //操作数 always@(opcode or a or b) //电平敏感的always 块 例6 用always 过程语句描述的简单算术逻辑单元 begin case(opcode) `add: out = a+b; //加操作 `minus: out = a-b; //减操作 `band: out = ab; //求与 `bor: out = a|b; //求或 `bnot: out=~a; //求反 default: out=8hx; //未收到指令时，输出任意态 endcase end endmodule 例7 用fork-join 并行块产生信号波形 `timescale 10ns/1ns module wave2; reg wave; parameter cycle=5; initial fork wave=0; #(cycle) wave=1; #(2*cycle) wave=0; #(3*cycle) wave=1; #(4*cycle) wave=0; #(5*cycle) wave=1; #(6*cycle) $finish; join initial $monitor($time,,,wave=%b,wave); endmodule 【例8】持续赋值方式定义的2 选1 多路选择器 module MUX21_1(out,a,b,sel); input a,b,sel; output out; assign out=(sel==0)?a:b; //持续赋值，如果sel 为0，则out=a ；否则out=b endmodule 【例9】阻塞赋值方式定义的2 选1 多路选择器 module MUX21_2(out,a,b,sel); input a,b,sel; output out; reg out; always@(a or b or sel) begin if(sel==0) out=a; //阻塞赋值 else out=b; end endmodule 例10 BCD 码—七段数码管显示译