一种高性能低复杂度的CAVLC编码器设计（陶为）.pdfVIP

第 卷 第 期 中国图象图形学报 Vol. ,No. 200 年 月 Journal of Image and Graphics .,200 一种高性能低复杂度的CAVLC编码器设计 1) 2) 3) 陶为 唐建 郭立 （中国科学技术大学电子科学与技术系，合肥，230027 ） 摘 要 提出了一种应用于H.264/AVC的高速有效的CAVLC编码器结构。为避免直接查找表，采用基于预处理的 查找方法，优化了查找表结构；对非零系数level编码，利用算术计算替代查找表，且通过展开和共享技术对算 术表达式进行优化；码字拼接部分也作了面积上的优化。在133MHz的频率约束下，采用SMIC 0.18um CMOS工艺 进行逻辑综合，所需的逻辑门数为8723，能满足高清视频1920×1088-30fps实时编码要求。 关键词 H.264/AVC 基于上下文的自适应变长编码CAVLC VLSI结构 中图法分类号：TN919.81 文献标识码：A 文章编号：1006-8961(200 ) - - A High Performance And Low Cost Implementation of CAVLC Encoder TAO Wei1), TANG Jian2), GUO Li3) (Department of Electronic Science and Technology, University of Science and Technology of China, Hefei, 230027) Abstract A high speed and efficient VLSI architecture for H.264/AVC CAVLC is proposed. For the sake of avoiding mapping look-up table directly, a new look-up table algorithm based on the pre-processing greatly optimizes look-up table structure; for non-zero coefficient level coding, an approach called arithmetic compute is exploited to replace look-up table, and the arithmetic expression is optimized with technology of unfolding and share ；And some optimization of area is done in the bit-packer module. With the synthesis constraint of 133MHz, the hardware cost of the proposed design is 8723 gates based on SMIC 0.18um CMOS technolo