Holistic Hardware Counter Performance Analysis of Parallel Programs.pdf

1 Holistic Hardware Counter Performance Analysis of Parallel Programs a a a Brian J. N. Wylie , Bernd Mohr , Felix Wolf aJohn von Neumann Institute for Computing, Forschungszentrum J¨ulich, D-52425 J¨ulich, Germany The KOJAK toolkit has been augmented with refined hardware performance counter support, in- cluding more convenient measurement specification, additional metric derivations and hierarchical structuring, and an extended algebra for integrating multiple experiments. Comprehensive auto- mated analysis of a hybrid OpenMP/MPI parallel program is demonstrated with performance exper- iments, containing communication and synchronisation metrics combined with a rich set of counter metrics, which provide a holistic analysis context and facilitate multi-platform comparison. 1. Introduction Modern microprocessors have integrated event counters which offer low-overhead access to a po- tential wealth of execution performance information, encompassing the utilisation and efficiency of various functional units and the memory and cache hierarchy. Although microprocessors from differ- ent manufacturers, and also within microprocessor families, provide broadly similar functionality, there are often very significant differences: variation in processor architecture and memory/cache hierarchy are reflected in corresponding event provision, and when combined with restrictions on which events may be measured simultaneously (and limited numbers of event counters) this greatly complicates performance measurement and analysis. Various libraries have addressed the measurement issues, providing a portable application pro- gramming interface to event counter control and access (e.g., PAPI [6]). Along with interfacing to system libraries, these offer standardised definitions for t