Impact of lineedge roughness on resistance and capacitance of scaled interconnects.pdf

Microelectronic Engineering 84 (2007) 2733–2737 /locate/mee Impact of line-edge roughness on resistance and capacitance of scaled interconnects M. Stucchi a,*, M. Bamal a,b, K. Maex b a IMEC, IPSI, Kapeldreef 75, B-3001 Leuven, Belgium b ESAT-INSYS, Kapeldreef 75, B-3001 Leuven, Belgium Received 10 May 2007; accepted 21 May 2007 Available online 2 June 2007 Abstract The impact of line-edge roughness (LER) on resistance R and capacitance C of on-chip interconnects is for the first time evaluated by a simulation methodology based on a realistic modeling of LER. The model can be calibrated with measured LER parameters. A geometrical approximations of LER is generated and superimposed to an interconnect architecture model with no roughness; resistance and capacitance are extracted from the model by a 3D static solver to estimate the impact of LER on them. By applying this methodology to the interconnect scaling scenario of the 2005 ITRS Roadmap, a small but increasing detrimental effect of LER on both R and C is predicted. 2007 Elsevier B.V. All rights reserved. Keywords: Interconnect resistance and capacitance; Line edge roughness; Technology scaling 1. Introduction Laplace equations of electrostatics, to directly evaluate the impact of LER on both resistance and capacitance of Line-edge roughness (LER) and the