SystemVerilog硬件设计及建模第789章.ppt

* * * * Sections 9.6-9.8 can be referred chapter5 and chapter6 * * * * The only difference is that nested modules is local, not global. pls. give the hierarchy diagram of the example. * * 网表是用线网将端口连接起来的模块实例的列表 verbose: 冗长，啰嗦 * * * * * * * * * * * * * * * * * * * * * * * Variables cannot be aliased. * * * * * do statements while (condition); * do statements while (condition); * do statements while (condition); * * * 在end后面可以跟着一个与对应的begin相同的块名，增加可读性！！！ * * * * * * * * * * * * * * * * 我的确有一个问题：综合后门级不会出现条件选项以外的情况？ * * * 结合前面的例子说明！！！ * * * * * * Draw a picture to show the architecture of module chip It is not common that multiple modules are placed in a file * 9.4.1 Implicit .name port connections register_files regs ( .dout(reg_file_out), .tmr0_reg, .status_reg, .fsr_reg, .port_a, .port_b, .port_c, .trisa, .trisb, .trisc, .option_reg, .w_reg, .instruct_reg, 9.4.1 Implicit .name port connections .program_data, .port_a_pins, .data_bus, .address(reg_file_addr), .clk, .resetN, .skip, .reg_file_sel, .zero_enable, .carry_enable, .w_reg_enable, .reg_file_enable, .zero, .carry, 9.4.1 Implicit .name port connections .special_reg_sel, .isoption,