Impact Ionization in InAlAshCaAs HFET ’ s.pdfVIP

IEEE ELECTRON DEVICE LETERS, VOL. 15, NO. 8, AUGUST 1994 313 Impact Ionization in InAlAshCaAs HFET’s A. A. Moolji, S. R. Bahl, Member, IEEE, and J. A. del Alamo. Senior Member IEEE Abstract-The presence of an energy barrier to the transfer of to experimentally study impact ionization in InAlAsAnGaAs holes from the channel to the gate electrode of InAlAdnGaAs HFET’s on InP. HFET’s prevents the gate current from being a reliable indicator The device structure utilized in this work has been described of impact ionization. Consequently, we have used a specially designed sidegate structure to demonstrate that due to the nar- in [14]. It consists of a 300 undoped Ino.41Alo.59Asstrained row bandgap of InGaAs, impact ionization takes place in the pseudoinsulator layer and a 100 A heavily doped (8 x 10l8 channel of these devices under normal operating conditions. The cm-3 Si) Ino.53G~.47Asactive channel, latticed-matched to ionization coefficient was found to follow a classic exponential InP. The fabrication details for these HFET’s have been dependence on the inverse electric field at the drain end of the reported in [15]. An important feature of the process is mesa gate, for over three orders of magnitude. sidewall isolation which was performed as described in [16]. All the measurements reported here were made on a sidegate structure which consists of an HFET (LG = 2