System Synthesis Utilizing a Layered Functional Model.pdfVIP

System Synthesis Utilizing a Layered Functional Model Ingo Sander Axel Jantsch Department of Electronics Department of Electronics Royal Institute of Technology Royal Institute of Technology Stockholm, Sweden Stockholm, Sweden ingo@ele.kth.se axel@ele.kth.se ABSTRACT buffers and the interconnect architecture between processes. The We propose a system synthesis method which bridges the gap resulting design decisions are explicit inputs to the synthesis between a highly abstract functional model and an efficient hard- process which fills in all the details implied by the design decisions ware or software implementation. The functional model is based on and the functional model. The synthesis deals with several aspects, a formal semantics and the synchrony hypothesis. However, the use i.e. skeletons, elementary functions, timing model, lists and data of skeletons in conjunction with a proper computational model types, and communication. The result is synthesizable VHDL and structures the system description into three layers, the system layer, C code. However, in this paper we focus mainly on hardware the skeleton layer, and the elementary layer. The synthesis process synthesis of skeletons and elementary functions. takes advantage of this structure and uses a different technique for The next section discusses related work, Section 3 gives an each layer: (a) connection of components and processes at the sys-