《《inverter layout Cadence_tutorial》.pdf

CMOS Inverter Layout Purpose Create New Library Create Layout Cell view NMOS Layout PMOS Layout Power Rails Connections and Labels DRC Schematic and LVS Netlist Extraction Purpose This tutorial is to walk you through the entire steps of a practice layout for those of you who are a new or inexperienced cadence user. The CMOS inverter circuit is a basic and simple circuit and thus it is appropriate for such a practice. The circuit schematic is shown below: Figure 1 CMOS inverter schematic Here, M1 is a NMOS transistor and M2 is a PMOS transistor. The Drain terminals of M1 and M2 are tied together (shorted) and they serve as the output terminal of the inverter. The Gate terminals of M1 and M2 are tied together and serve as the input terminal. The Source terminal of M1 (NMOS) is grounded (GND!) and Source of M2 (PMOS) is connected to the supply (Vdd!) voltage. The Source of each transistor is shorted to the Body of each transistor. In this tutorial, we use a channel width of 4.0um and channel length of 1.6um for NMOS and width=10um, length=1.6um for PMOS in the MOSIS SCMOS (Scalable CMOS) 1.5um process. For details of the SCMOS process, refer to the MOSIS website /Technical/Layermaps/lm-scmos_scna.html. To start, run the cadence by typing icfb at the unix prompt (per step.8 of the ENG Account setup instruction). After you start the cadence, CIW (Command Interpreter Window) and Library Manager will appear as shown in Fig.2 and Fig.3. Figure2 CIW window Figure3 Library Manager Window Create new Library 1. In the Library Manager, File ‡New ‡Library 2. Type the name of library of your choice in the name field, e.g., tutorial” , in the Name field of ‘Create Library’ popup window, as shown in Fig.4. 3. In the Technology Library field, select the option Attach to existing tech