《《电子信息工程专业英语翻译清华出版社English_for_IT_and_EE-02》.ppt

《《电子信息工程专业英语翻译清华出版社English_for_IT_and_EE-02》.ppt

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《《电子信息工程专业英语翻译清华出版社English_for_IT_and_EE-02》.ppt

* 2 Modern ASICs often include entire 32-bit processors, memory blocks including ROM, RAM, EEPROM, Flash and other large building blocks. Such an ASIC is often termed a SoC (System-on-Chip). Designers of digital ASICs use a hardware description language (HDL), such as Verilog or VHDL, to describe the functionality of ASICs. 现代ASIC常包含32位处理器,包括ROM、RAM、EEPROM、Flash等存储器,以及其它大规模组件。 * 3 Field-programmable gate arrays (FPGA) are the modern day equivalent of 7400 series logic and a breadboard, containing programmable logic blocks and programmable interconnects that allow the same FPGA to be used in many different applications. For smaller designs and/or lower production volumes, FPGAs may be more cost effective than an ASIC design. 7400系列和面包板的现代版 较小规模的设计或(与)小批量生产 * 3 The non-recurring engineering cost (the cost to setup the factory to produce a particular ASIC) can run into hundreds of thousands of dollars.2 不能循环的工程费用(建立工厂生产特定ASIC的成本)可能会达到数十万美元。 * 4 The general term application specific integrated circuit includes FPGAs, but most designers use ASIC only for non-field programmable devices and make a distinction between ASIC and FPGAs.3 专用集成电路这一通用名词也包括FPGA,但是大多数设计者仅将ASIC用于非现场可编程的器件,将ASIC和FPGA两者区别开来。 * 5 History The initial ASICs used gate array technology. Ferranti produced perhaps the first gate-array, the ULA (Uncommitted Logic Array), around 1980. Customization occurred by varying the metal interconnect mask. ULAs had complexities of up to a few thousand gates. Later versions became more generalized, with different base dies customized by both metal and polysilicon layers. Some base dies include RAM elements. 多至几千个门电路的复杂度 适应用户的包含金属和多层硅的不同基底 * 6 Standard cell design In the mid 1980s a designer would choose an ASIC manufacturer and implement their design using the design tools available from the manufacturer. While third party design tools were available, there was not an effective link from the third party design tools to the layout and actual semiconductor process perf

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