《03.Enhanced thermoelectric performance of rough silicon nanowires》.pdf

doi: 10.1038/nature06458 SUPPLEMENTARY INFORMATION Silicon Nanowires as Highly Efficient Thermoelectric Materials― Supplementary Information (Experiment) Akram I. Boukai#, Yuri Bunimovich#, Jamil Tahir-Kheli, Jen-Kan Yu, William A. Goddard III, and James R. Heath* Device Fabrication and Measurement Setup The devices used in this report were fabricated from intrinsic silicon-on-insulator (SOI) substrates (Ibis Technology) with a buried oxide thickness of 150nm. The top Si(100) epilayer began with a thickness of 400nm and was thinned through repeated thermal oxidations nn 55 and wet chemical etching steps until the oo ii tt desired Si layer thickness (20nm or 35nm) aa rr )) tt 33 nn --mm was obtained. AFM analysis revealed a ee cc cc nn 99 33 smooth surface with an rms roughness of oo 11 00 CC 11 tt xx ~3.6 Å. Next, the Si epilayer was doped nn (( aa pp 11