《2016 Rigel A 1024-Core Single-Chip Accelerator Architecture》.pdf

RIGEL: A 1,024-CORE SINGLE-CHIP ACCELERATOR ARCHITECTURE RIGEL IS A SINGLE-CHIP ACCELERATOR ARCHITECTURE WITH 1,024 INDEPENDENT PROCESSING CORES TARGETED AT A BROAD CLASS OF DATA- AND TASK-PARALLEL COMPUTATION. THIS ARTICLE DISCUSSES RIGEL’S MOTIVATION, EVALUATES ITS PERFORMANCE SCALABILITY AS WELL AS POWER AND AREA REQUIREMENTS , AND EXPLORES MEMORY SYSTEMS IN THE CONTEXT OF 1,024-CORE SINGLE-CHIP ACCELERATORS. THE AUTHORS ALSO CONSIDER FUTURE OPPORTUNITIES AND CHALLENGES FOR LARGE-SCALE DESIGNS. Increasing demand for perfor- such as control and instruction fetch across mance on data-intensive parallel workloads many processing elements. However, when has driven the design of throughput-oriented applications don’t naturally map to the parallel compute accelerators. For this work, SIMD execution model, programmers must we consider programmable accelerators in adapt their algorithms or suffer reduced effi- Daniel R. Johnson contrast to fixed-function or hardwired ciency. SIMD then limits the scope of appli- application-specific accelerator units. Cur- cations that can achieve the hardware’s peak Matthew R. Johnson rent programma