《SN74CBTD3384C》.pdf

SCDS133A −SEPTEMBER 2003 − REVISED OCTOBER 2003 Undershoot Protection for Off-Isolation on Data I/Os Support 0 to 5-V Signaling Levels A and B Ports Up To −2 V (0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V) Integrated Diode to VCC Provides 5-V Input Control Inputs Can be Driven by TTL or Down To 3.3-V Output Level Shift 5-V/3.3-V CMOS Outputs Bidirectional Data Flow, With Near-Zero Ioff Supports Partial-Power-Down Mode Propagation Delay Operation Low ON-State Resistance (ron) Latch-Up Performance Exceeds 100 mA Per Characteristics (ron = 3 Ω Typical) JESD 78, Class II Low Input/Output Capacitance Minimizes ESD Performance Tested Per JESD 22 Loading and Signal Distortion − 2000-V Human-Body Model (Cio(OFF) = 5 pF Typical) (A114-B, Class II) Data and Control Inputs Provide − 1000-V Charged-Device Model (C101) Undershoot Clamp Diodes Supports Both Digital and Analog VCC Operating Range From 4.5 V to 5.5 V Applications: Memory Interleaving, Bus Isolation, Low-Distortion Signal Gating DB, DBQ, DGV, DW, OR PW PACKAGE