《XC95144XL_10TQ100C-9750552》.pdf

0 R XC95144XL High Performance CPLD DS056 (v1.5) August 21, 2003 0 5 Preliminary Product Specification Features Power Estimation • 5 ns pin-to-pin logic delays Power dissipation in CPLDs can vary substantially depend- • System frequency up to 178 MHz ing on the system frequency, design application and output • 144 macrocells with 3,200 usable gates loading. To help reduce power dissipation, each macrocell • Available in small footprint packages in a XC9500XL device may be configured for low-power - 100-pin TQFP (81 user I/O pins) mode (from the default high-performance mode). In addi- - 144-pin TQFP (117 user I/O pins) tion, unused product-terms and macrocells are automati- cally deactivated by the software to further conserve power. - 144-CSP (117 user I/O pins) • Optimized for high-performance 3.3V systems For a general estimate of ICC, the following equation may be - Low power operation used: - 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V ICC(mA) = MCHS(0.175*PTHS + 0.345) + MCLP(0.052*PTLP signals + 0.272) + 0.04 * MCTOG(MCHS +MCLP)* f - 3.3V or 2.5V output capability where: - Advanced