《03_IC_Packaging_SiP_165_roadmap》.pdf

I N V E Allegro 16.5 - What’s New Cadence SiP co-design and IC Packaging N T Brad Griffin I Allegro Product Management V E Agenda • Industry Trends • Cadence SiP and APD Version 16.5 – What’s new overview – Details • Roadmap © 2010 Cadence Design Systems, Inc. All rights reserved. 2 Industry trends Smaller / Denser, Faster, Cheaper BGA family WLCSP FBGA QFP (mini BGA) family BCC SiP BGA SOP P-DIP family Courtesy ASE Package- Thru SiP with Si Wirebond Flip Chip Stacked Die on-Package Silicon Vias Interposer PCI 2.0 PCI 2.1 PCI-X 1.0 PCI-X 2.0 PCIe PCIe 2.0 PCIe 3.0 33 MHz 66 MHz 133 MHz 266 MHz 2.5 Gbps 5 Gbps 8 Gbps 1990 1995 2000 2005 2011 © 2010 Cadence Design Systems, Inc. All rights reserved. 3 Cadence SiP and APD – 16.5 Release What is new? FCS - TBD Cadence APD and SiP – All tiers • Wirebonding improvements • BGA footprint report (Excel) • Embedded component support • Usability improvements • Highlighting, pin/finger selection, symbol editor,