《Bump formation for flip chip and CSP by solder paste printing》.pdf

Microelectronics Reliability 42 (2002) 391–398 /locate/microrel Bump formation for flip chip and CSP by solder paste printing Joachim Kloeser a,*, Paradiso Coskina b, Rolf Aschenbrenner b, Herbert Reichl b a € EKRA GmbH Maschinenfabrik, Zeppelinstrasse 16, D-74357 Boonnigheim, Germany b Fraunhofer Institute FhG/IZM-Berlin, Department of Chip-Interconnection Technologies and Advanced Packages, D-133 Berlin, Germany Received 24 May 2001; received in revised form 30 July 2001 Abstract Area array packages (flip chip, CSP and BGA) require the formation of bumps for the board assembly. Since the established bumping methods need expensive equipment or are limited by the throughput, minimal pitch and yield the industry is currently searching for new and lower cost bumping approaches. In this paper the experi- mental work of stencil printing to create solder bumps for flip chip and wafer level CSP (CSP-WL) is described in detail. This paper is divided into two parts. In the first part of the paper a low cost wafer bumping process for flip chip applications will be studied in particular. The process is based on an electroless Nickel under bump metallization and solder bumping by stencil printing. The experimental results for this technology will be presented and the limits con- cerning pitch, reproducibility and bump height will be discussed in detail. The second part of the paper is focused on solder paste printing for wafer-level CSPs. In order to achieve large bumps an o