《DDR2与DDR3信号完整性及PCB设计》.pdf

Signal Integrity and PCB layout considerations for DDR2-800 Mb/s and DDR3 Memories Fidus Systems Inc. 900, Morrison Drive, Ottawa, Ontario, K2H 8K7, Canada Chris Brennan, Cristian Tudor, Eric Schroeter, Heike Wunschmann, and Syed Bokhari Session # 8.13 Abstract The paper addresses the challenge of meeting Signal Integrity (SI) and Power Integrity (PI) requirements of Printed Circuit Boards (PCBs) containing Double Data Rate 2 (DDR2) memories. The emphasis is on low layer count PCBs, typically 4-6 layers using conventional technology. Some design guidelines have been provided. 1. Introduction DDR2 usage is common today with a push towards higher speeds such as 800 Mbps [1] and more recently, 1066 Mbps. DDR3 [2] targets a data rate of 1600 Mbps. From a PCB implementation standpoint, a primary requirement is delay matching which is dictated by the timing requirement. This brings into it a number of related factors that affect waveform integrity and delay. These factors are interdependent, but where a distinction can be made, they can be termed PCB layer stackup and impedance, interconnect topologies, delay matching, cross talk, PI and timing. Cadence ALLEGRO™SI-230 and Ansoft’s HFSS™ are used in all computations. VDD / Vref VDD / Vtt / Vref Clock CKP,CKN Address ADDR15,0 Command/ Control CKE, CS, ODT, RAS,CAS,WE,BA0-2 DataStrobe (differential) DQS0,DQS1,DQS2,DQS3 DataMask