《ECEB368 Project One DB129281》.docx

ECEB368 Project One--Basic CMOS Amplifier Design D-B1-2928-1 Tang Qi Summary M1M2Av(dB)GBW(MHz)wlVB(mV)wlVBsim resultcal resulterrorsim resultcal resulterrorCS14.320.186009.320.0960021.1629.50139.22%899.4900.0M0.067%CG13.520.1860060.1860020.562.21989.2%573.4577.30.68%CD400.18600350.18450-1.378-0.567958.79%858.475512.05%Introduction In this project, three kinds of basic CMOS amplifiers will be built in Cadence. They are designed to reach the specifications as below. As the similarity of bipolar and MOS small signal models suggests that the same must hold for MOS amplifiers, three basic CMOS amplifiers are accepted. They are common-source (CS) stage, common-gate stage, and common-drain (CD) stage, or source follower. These three basic CMOS amplifiers are designed as Fig.01 shows. CSCGCDgain20dB20dB-2dBGBW400MHz400MHz600MHzpower consumption1mW1mW1mWsupply voltage1.2V1.2V1.2Vcapacitive load1pF1pF1pFnoiseTHDminimizedminimizedminimized Table.01 Common Source Amplifier The main aim is to adjust the characteristics of w, l, (m, and nfing) to satisfy that gain larger than 20dB and GBW larger than 400MHz (power consumption controlled). By theoretical analysis and practical trials, we will find several ways to achieve this. First, build the circuit, do the packaging and set tests, as shown in Fig.01 Fig.02. Fig.01 CS_amp_schemetic Fig.02 CS_Test circuit Initially, the default values of the PMOS NMOS from the tutorial are: wlmnfingPMOS120.1818NMOS2.80.0914Table.02 However, the default settings could not satisfy the requirement that gain20dB for the GAIN is a lot smaller than expected 20dB. Fig.03 initial setting simulation result Trial 2, we multiplied 1.2 to w l of PMOS and then get GAIN=19.17 and GBW=461.4M. Analysis- DC: The simulation analysis with initial value from the cadence outputs the following list: Fig.03 DC operation data of NMOS of CS