基于fpga的数字调制解调器设计__学士学位论文.doc

基于FPGA的数字调制解调器设计 摘要 本设计使用FPGA在EDA技术开发QuartusⅡ上实现以正弦信号为载波的三种调制信号ASK、FSK、PSK的和解调。系统采用ALTERA公司生产的DE2开发板，Cyclone II EP2C35F672C6型号的FPGA和EPCS16系列的配置驱动，系统时钟为50MHZ，经四分频产生一路时钟信号经过DDS波形发生器形成ASKPSK及FSK的一路载波，FSK的另一路载波由系统时钟经八分频后经过DDS波形发生器后产生。由于ASK和PSK调制特性相近，载波都为一路信号。因此在设计时将ASK和PSK调制放在模块里设计，用一个选择键和两个基带信号控制端来控制。系统时钟经过512分频后经过随机信号模块产生一路周期为15的伪随机序列作为数字调制的基带信号。在解调时，用非相干解调法解调ASK和PSK信号，用过零检测法解调FSK信号。FPGA, ASK, PSK, FSK  Digital modulation and demodulation based on FPGA Abstract This design uses FPGA on EDA technology development platform QuartusⅡ to achieve the generation and the demodulation of three modulation signal——ASK,FSK,PSK as carrier through sinusoidal signals.The system uses the ALTERA companys DE2 development board,FPGA of Type Cyclone II EP2C35F672C6FPGA and driver configuration of EPCS16 series.This system is realized in VHDL hardware description language,whose ASK,PSK and FSK carrier is generated when the four frequency produces a clock signal through the DDS waveform generator,and the system clock is 50MHZ.Because the characteristics of ASK and PSK modulation are similar to each other,which means their carrier are both one way signal,the modulation of ASK and PSK are put on the same model when designed,with a selection key and the two baseband signal control ends controlling.System clock generates pseudo random sequence baseband signals whose one road cycle is 15 as baseband signals through random signal model after the 512 frequency division.When in modulation,we use non coherent demodulation to demodulate ASK and PSK signal,and the zero crossing detection method for FSK signal demodulation.After the system is tested through the function simulation and verification,whether the output signal and the baseband signal are conformed to each other or not will be tested Key words: FPGA, ASK, PSK, FSK目录 1 绪论 1 1.1 课题背景与研究现状 1 1.1.1数字调制解调背景知识 1 1.1.2 FPGA背景知识 2 1.2 课题的主要研究工作 4 1.3 本论文的结构 4 2.EDA技术简介 6 2.1 Quartus II 简介 6 2.1.1 Quartus II的使用及主要设计流程 7 2.1.2 Quartus II的原理图输入设计流程