FPGA课程设计物联网.doc

CPLD/FPGA课程设计 项目名称 基于FPGA的IIC接口设计与实现 专业班级 物联网112班 学生学号 2011133056 学生姓名 王海超 指导教师 苗凤娟 2014年月 日 摘要 关键词： Abstract IIC (Inter Integrated Circuits) Bus is developed by Philips for the connection between the chip serial bus. In the digital ASIC design, Field-programmable gate array (FPGA) design has been widely used because of its flexibility and high speed. The main task of IIC serial bus interface circuit design is based on the IIC timing agreement with Verilog HDL language description of the IIC bus interface circuit, which aims to achieve IIC interface circuit up to comprehend complex digital circuit design ideas and concepts through the FPGA. Based on the in-depth research of the IIC bus status and development, the design scheme of the random read/write IIC interface circuit on FPGA was underlined in the paper. First,hardware description language (Verilog HDL) and field-programmable gate array (FPGA) were introduced slightly in the paper. Second, the internal structure and data transmission format of IIC serial bus and its timing protocol were illustrated in the paper in detail. Based on this, the interface circuit design in FPGA development board was emphasized in the paper.As well as, the simulation and test of data transmission with peripheral devices EEPROM with IIC interface were stressed. After several experiments, IIC bus interface circuit has passed the behavioral level simulation and synthesis and layout-level timing simulation backdoor to meet system requirements. Finally, the research results were summarized. Therefore, this lesson set selection sequence interface module to study them. The keyword: Verilog_HDL; FPGA; IICserial bus ; Random read /write; EEPROM; The sequential interface 目录 摘要 I Abstract II 目录 III 第1章 1 1.1 概述 1 1.2 IIC接口设计的研究现状 1 1.2.1 IIC接口设计的应用 1 1.2.2 I2C接口设计的困难 1 1.3 本文研究的意义 2 1.4发展趋势 2 第2章 Verilog HDL和FPGA的简介 3