8路抢答器的VHDL语言.docVIP

八路抢答器由优先编码电路、锁存器、译码电路将输出主持人开关启动 顶层文件原理图： VHDL程序： library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity myproject is port( clk : in std_logic; --时钟信号 clear : in std_logic; --清零信号 player : in std_logic_vector(7 downto 0); --八个抢答选手输入 settime1 : in std_logic_vector(3 downto 0);--答题时间设置 led_10s : out std_logic_vector(6 downto 0); --10s抢答计时已进行的时间显示 selector : out std_logic_vector(6 downto 0); --抢中选手编码输出 audio : out std_logic; --喇叭响,低有效. endanswer : in std_logic; --答题完成 led_left1 : out std_logic_vector(6 downto 0) ); end myproject; architecture Behavioral of myproject is component qiangda port( set_start : in std_logic; a : in std_logic_vector(7 downto 0); clk : in std_logic; led : out std_logic_vector(6 downto 0); selector : out std_logic_vector(6 downto 0); selected : out std_logic; alarm : out std_logic ); end component; component dingshiqi port( selected : in std_logic; clk : in std_logic; settime1: in std_logic_vector(3 downto 0); endanswer : in std_logic; alarm : out std_logic; led : out std_logic_vector(6 downto 0) ); end component; component baojing port( clk : in std_logic; alarm1 : in std_logic; alarm2 : in std_logic; alarm3 : in std_logic; audioer : out std_logic ); end component; signal selected1 : std_logic; signal start : std_logic:=0; signal alarm1 : std_logic:=0; signal alarm2 : std_logic; begin startall : process(clear) begin if clearevent and clear=1 then start=not start; end if; end process; u1: qiangda port map(start,player,clk,led_10s,selector,selected1,alarm1);