时序分析之1静态分析基础.pdf

QuartusQuartus®® II Software DesignII Software Design Series: Timing AnalysisSeries: Timing Analysis -- Timing analysis basicsTiming analysis basics © 2009 Altera Corporation 1 ObjectivesObjectives n Display a complete understanding of timing analysis © 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 2 How does timing verification work?How does timing verification work? n Every device path in design must be analyzed with respect to timing specifications/requirements - Catch timing-related errors faster and easier than gate-level simulation board testing n Designer must enter timing requirements exceptions - Used to guide fitter during placement routing - Used to compare against actual results PRE PRE IN ® D Q ® D Q ® OUT CLK CLR CLR CLR combinational delays © 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 3 Timing Analysis BasicsTiming Analysis Basics n Launch vs. latch edges n Setup hold times n Data clock arrival time n Data required time n Setup hold slack analysis n I/O analysis n Recovery removal n Timing models © 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 4 Path Analysis TypesPath Analysis Types Async Path PRE Data Path