Hybrid CompilerHardwarePrefetching for Multiprocessors Using.pdf

/ Hybrid Compiler/Hardware Prefetching for Multiprocessors Using Low-Overhead Cache Miss Traps Jonas Skeppstedt and Michel Dubois CENG Technical Report 97-04 Department of Electrical Engineering-Systems University of Southern California Los Angeles, California 90089-2562 (213)740-4475 February 1997 Hybrid Compiler/Hardware Prefetching for Multiprocessors Using Low-Overhead Cache Miss Traps Jonas Skeppstedt and Michel Dubois Department of Computer Engineering Department of Electrical Engineering-Systems Chalmers University of Technology University of Southern California S-412 96 Gothenburg, SWEDEN Los Angeles, CA 90089-2562, USA jonas@ dubois@ Abstract In this paper we propose and evaluate a new data-prefetching technique for cache co herent multiprocessors. Prefetches arc issued by a new functional unit called a prefetch en gine which is controlled by the compiler. We let second-level cache misses generate cache miss traps, and start the prefetch engine in a trap handler. The trap handler is fast (40-50 cycles) and does not normally delay the program beyond th