Integrated LFSR Reseeding, Test-Access Optimization, and Test.pdfVIP

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 28, NO. 8, AUGUST 2009 1251 Integrated LFSR Reseeding, Test-Access Optimization, and Test Scheduling for Core-Based System-on-Chip Zhanglei Wang, Krishnendu Chakrabarty, Fellow, IEEE, and Seongmoon Wang Abstract—We present a system-on-chip (SOC) testing approach techniques also depends on the number and lengths of scan that integrates test data compression, test-access mechanism/test chains. However, some SOC chips contain IP cores or black wrapper design, and test scheduling. An efficient linear feedback box cores that are not provided to the system integrator with shift register (LFSR) reseeding technique is used as the com- pression engine. All cores on the SOC share a single on-chip detailed structural information [5]. Many SOCs also include LFSR. At any clock cycle, one or more cores can simultaneously hard cores that are delivered in the form of layouts such that receive data from the LFSR. Seeds for the LFSR are computed the configurations of scan chains cannot be modified. Existing from the care bits for the test cubes for multiple cores. We also compression techniques for stand-alone ICs are, therefore, less propose a scan-slice-based scheduling algorithm that attempts to efficient for such SOCs. maximize the number of care bits the LFSR can produce at each clock cycle, such that the overall test application time (TAT) is In addition to the problem of limited applicability of existing minimized. This scheduling method is static in nature because test compression techniques, restricted access to internal cores it requ