数字相机时序模拟技术研究解析.doc

摘 要 近年来0.13μm工艺），芯片单位面积集成度迅猛提高。受益于此，可编程逻辑器件（PLD）功耗低、体积小、集成度高、速度快及可重复编程和擦写等优点(FPGA)和复杂可编程逻辑器件(CPLD)。CMOS数字相机中时序的应用。 本文根据CMOS图像传感器芯片OV7620的工作原理和特点设计了一个数字相机时序模拟电路。该电路将模拟出CMOS图像传感器芯片OV7620的像素时钟、行同步和帧同步信号，并与上位机连接，实现图像灰度值的数据传输。论文最后给出了数字相机时序的测试和实验得到的结果，并对其进行了简单的分析。 关键词：数字相机 时序 模拟 可编程逻辑器件 图像传感器 Abstract In recent years, chip unit area integration rate swiftly and the chip manufacture craft promotion enhance violently(at present the 0.13μm craft has been used massively).Profits in this, programmable logical component(PLD) could develop swiftly and violently, enhancing merits as low power loss, the small volume, the high integration rate, the speed quickly, duplicate programs and scratches writes and so on. The widest application one of PLD is scene programmable gate array (FPGA) and complex programmable logical component (CPLD).The main research of this article is the application of CPLD at timing of the CMOS digital camera. This article has designed a section quite complete digital camera timing simulating circuit according to CMOS the image sensor chip OV7620.The circuit will analog the picture element clock, row synchronization and frame synchronization signal of CMOS the image sensor chip OV7620, and connect with computer, transmit the gradation value data of the picture. The paper finally has produced the result which the digital camera timing test and the experiment debugs obtains, and has carried on the simple analysis to it. Keywords: Digital camera Timing Simulating Complex pogrammable logic device Image sensor 目 录 第一章 绪 论 1 1.1数字相机的背景 1 1.2数字相机时序模拟技术研究的意义 2 1.3数字相机时序模拟技术研究的现状 3 1.4数字相机时序模拟技术研究的主要内容 3 第二章 CMOS图像传感器原理及其时序模拟 4 2.1 CMOS图像传感器像元结构的种类 4 2.2 CMOS图像传感器OV7620 6 2.3 可编程逻辑器件 9 2.4 对CMOS图像传感器时序模拟的意义 11 第三章 时序模拟电路硬件组成 13 3.1 EPM7128芯片 14 3.2 AVR单片机AT90S8515 15 3.3 USB接口器件PDIUSBD12 16 3.4 静态存储器HM628512 17 第四章 时序模拟软件原理分析 19 4.1 模拟时序要求 19 4.2 设计方案及实验结果 20 4.3 时序信号的对比 25 第五章 硬件电路设计及测试结果 28 5.1 硬件电路设计 28 5.2 测试结果 29 结 论 34 参考文献 35 致 谢 36 1.1数字相机的背景