slides-Microarch.org.ppt

Application-Specific Processing on a General Purpose Core via Transparent Instruction Set Customization Nathan Clark, Manjunath Kudlur, Hyunchul Park, Scott Mahlke, Krisztián Flautner* Advanced Computer Architecture Lab, University of Michigan *ARM Ltd. A Case for Customization General purpose processors handles many applications fairly well, but… Each application has different requirements Need for efficient execution Impressive design wins through customization Performance, power, area Up to 3.5x speedup [Hot Chips 16] Instruction Set Customization Traditional vs. Transparent Customization High Non-Recurring Engineering costs (NRE) “Universal” accelerator No ISA change Design of a Compute Accelerator Goal: support important computation subgraphs Array of function units Exploits subgraph parallelism Allows natural data propagation CCA Shape CCA Shape CCA Utilization CCA Operations Dynamic opcodes in important subgraphs Excluded mpy/div, load/store, branch Two main categories – logicals, adds Subgraphs rarely have more than 3 dependent adds Proposed CCA Design 4 inputs/2 outputs Two FU types Arith/logic Logic Crossbar between rows Captures 99% of important subgraphs Synthesis of CCA Synopsys design tools, 130nm library CCA Utilization Dynamic Selection – Dynamic Realization Detect and replace subgraphs in fill unit of trace cache Simulation SimpleScalar – ARM instruction set 4-wide Execution, 1 compute accelerator 128 RUU entries 32k inst. trace cache, 256 inst. Traces 5000 cycle selection/insert latency L1 I-cache : 32k, 2 way, 2 cycle hit L1 D-cache : 32k, 4 way, 2 cycle hit Varying CCA Latency Static Selection – Dynamic Realization Compiler selects subgraphs offline Communicated to the hardware at load time Control bits stored in a table and inserted at decode Dynamic vs. Static Selection Summary Transparent instruction set customization Benefits of customization without changing ISA Presented design of a compute accelerator Handle majority of important