VL7301.doc-SriVenkateswaraCollegeofEngineering.doc

Department of Electronics and Communication Engineering LP: VL7301 Rev. No: 01 Date: 01.07.2015 M.E : EC Regulation: 2013 PG Specialization : APPLIED ELECTRONICS Sub. Code / Sub. Name : VL7301 TESTING OF VLSI CIRCUITS Unit : I UNIT I TESTING AND FAULT MODELLING 9 Introduction to testing – Faults in Digital Circuits – Modeling of faults – Logical Fault Models – Fault detection – Fault Location – Fault dominance – Logic simulation – Types of simulation – Delay models – Gate Level Event – driven simulation. Objective: To know the various types of faults and also to study about fault detection and dominance. Session No * Topics to be covered Ref Teaching Aids Introduction to testing - Need for testing 1-Ch-1 pg.9-10, 4-Ch-4 pg.57-60 PPT Faults in Digital Circuits 1-Ch-4 pg.93, 4-Ch-4 pg.60 2-Ch-2 pg.12-22 PPT Faults Modeling - Logical fault models 1-Ch-4 pg.93-95 PPT Fault Equivalence, Fault Detection - Combinational and Sequential circuits 1-Ch-4 pg. 95-106 PPT Fault Location - Combinational and Sequential circuits 1-Ch-4 pg. 106-108 PPT Fault Dominance - Combinational and Sequential circuits 1-Ch-4 pg. 109-110 PPT Logic simulation - Types of simulation 1-Ch-2 pg. 42-43 PPT Delay models 1-Ch-2 pg. 52-56 5-Ch-2 pg. 49 PPT Gate level Event-driven simulation 1-Ch-2 pg. 64-77, 4-Ch-5 pg. 101-103 PPT Content beyond syllabus covered (if any): Fault Equivalence – Combinational and Sequential circuits Course Outcome 1: To apply test pattern for the detection of logical fault. * Session duration: 50 minutes  Sub. Code / Sub. Name : VL7301 TESTING OF VLSI CIRCUITS Unit : II UNIT II TEST GENERATION 9 Test generation for combinational logic circuits – Testable combinational logic circuit design – Test generation for sequ