CPLD实现数码管动态.docVIP

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. ---- library UNISIM; ---- use UNISIM.VComponents.all; entity dynamic is Port ( clk,reset: in std_logic; din1 : in std_logic_vector(6 downto 0);--译码后的数据信号1 din2 : in std_logic_vector(6 downto 0); --译码后的数据信号2 din3 : in std_logic_vector(6 downto 0); --译码后的数据信号3 din4 : in std_logic_vector(6 downto 0); --译码后的数据信号4 shift: out std_logic_vector(3 downto 0); --位选信号 bus4 : out std_logic_vector(6 downto 0)); --数据信号 end dynamic; architecture Behavioral of dynamic is signal scan_clk:std_logic_vector(1 downto 0); begin process(clk,scan_clk,reset) --分频进程 variable scan:std_logic_vector(17 downto 0); begin if reset=1 then scan:=000000000000000000; scan_clk=00; elsif clkevent and clk=1then scan:=scan+1; end if; -- scan_clk=scan(1 downto 0); --this line for simulation scan_clk=scan(17 downto 16) --work on 100MHz CLOCK end process; process(scan_clk,din1,din2,din3,din4) --扫描进程 begin case scan_clk is when 00= bus4=din1;shift=0001; when 01=bus4=din2;shift=0010; when 10=bus4=din3;shift=0100; when 11=bus4=din4;shift=1000; when others= bus4=0000000;shift=0000; end case; end process; end Behavioral; LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY LED_dynamic_show_tb_vhd IS END LED_dynamic_show_tb_vhd; ARCHITECTURE behavior OF LED_dynamic_show_tb_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT dynamic PORT(clk : IN std_logic; reset : IN std_logic; din1 : IN std_logic_vector(6 downto 0); din2 : IN std_logic_vector(6 downto 0); din3 : IN std_logic_vector(6 downto 0); din4 : IN std_logic_vector(6