IBM e-business顶级、经典模版.pptVIP

A Semiconductor Supply Chain Model withNon-Stationary Parameters INFORMS Miami Beach, Florida November 4-7, 2001 Guillermo Gallego Columbia University Department of Industrial Engineering and Operations Research, City of New York ggallego@ Bala Ramachandran, Kaan Katircioglu IBM T.J.Watson Research Center Yorktown Heights, NY 10598 rbala@, kaan@ Sandy Anderson, Tracey Pilkinton, George Wood IBM Microelectronics Division Burlington, Vermont Environment: Semiconductor manufacturing/distribution supply chain has a global multi-echelon structure... Wafer Test Die Stock Bond and Assembly Test Module Substock Module Final Stock Card Assembly Card Final Stock Mfg/Assembly/Test location Physical stocking location typically 1.5-3 months typically 1-2 weeks typically 1 week Environment: Semiconductor Part Proliferation Choices: Design Level Tests: Wafer Sorts quality Tests Results: Reliability: Pass/Fail random Speed Sort: Random test results Die Stock Module Stock Wafer Mfg Test Bond Assembly Burn-In, Test Sort Packaging Options: Organization, Addressing, etc. Environment: Market Conditions Trends Moore’s law continues to hold i.e. 50% cost reduction in every 18 months Seasonal gyrations in demand/supply balance Power in hands of customers Increasingly stringent service requirements JIT, shorter order-to-delivery cycle times Contracts becoming common Constructive partnerships are rare Product life cycles are short and prices decline fast Commodity products have low margins Environment: Wafer Fabrication Objectives: Reduce cycle times WIP inventory Improve yields very significant cost driver Meet service commitments at die stock Maximize process learning Minimize unit production costs Achieve high capacity utilization Maximize quarterly vs. long-term profit Conflicting operations strategies: Start only what is needed vs. fill the line to capacity Push vs. Pull Keep lots moving vs. allow engineering holds Many Complex cons