Clock Gating-An Effective Low-Power Technique.ppt

Clock Gating An Effective Low-Power Technique Clock Gating An Effective Low-Power Technique “Clock Gating” An Effective Low-Power Technique Abdulkadir Utku Diril Seyed-Abdollah Aftabjahani? Georgia Institute of Technology RISC Architectures Fall 2001 Clock Gating Power Consumption Primitives Characteristics of Power Consumption in Microprocessors Clock Gating and Power Reduction Similar Approaches Power Reduction Example Power Consumption in Digital Systems P total P static + P dynamic Static Power Currently Negligible But Considerable in Future Dynamic Power P dynamic CL Vdd2.A.F Major Part of Total Power e.g. 95% Power Consumption Characteristics Clock Circuitry Power Consumption 15 to 45% of Total P clock circuitry ~ Frequency Activity of Functional Units A units 50% in Execution Time Power Consumption Characteristics Clock Gating and Power Reduction Main Idea Clock Circuitry Partitioning Shutting down Unused Partitions Implementation Creating Local Clocks Buffers or Flip-Flops with enable signal Net Effects Reduction of Unnecessary Switching Switched Capacitance Reduction of Clock Circuitry Power Consumption Reduction Clock Gating and Power Reduction cont. How to determine unused modules? Dynamically in Decode Stage Statically with Compiler Assistance Disadvantages Additional Circuitry More Complicated Timing Analysis, Design, Test and Verification Possible High L x di/dt Noise Similar Methods Data Gating Effective in Wide Modules Like ALUs Complicated Design Possible Increase of Critical Path Delay Powering Down Unused Modules Possible Long Wake-up Times Need of Compiler and/or OS Support Using Asynchronous Systems Unnecessary Activity Elimination Harder Design Power Reduction Example Summary Clock Gating as an Architectural Technique Turning Unused Parts of Circuit Off High P dynamic /P total Ratio Decrease of Activity to Reduce Power Considerable Power Reduction up to 25% Highly Used Technique * Execution Pipe Usage Ra