数字逻辑原理与实践3-2精讲.ppt

REVIEW OF LAST CLASS 3.4 Electrical Behavior of CMOS Circuits CMOS电路的电气特性 Logic voltage levels. 逻辑电压电平 DC noise margins 直流噪声容限 Fanout. 扇出 Speed, Power consumption 速度、功耗 Noise, Electrostatic discharge 噪声、静电放电 Open-drain outputs. Three-state outputs 漏极开路输出、三态输出 3.5.1 Logic Levels and Noise Margins 逻辑电平和噪声容限 CMOS逻辑系列（HC）电平规格 3.5.2 Circuit Behavior with Resistive Loads 带电阻性负载的电路特性 P103 3.5.2 Circuit Behavior with Resistive Loads 带电阻性负载的电路特性 P103 REMEMBERING THéVENIN Any two-terminal circuit consisting of only voltage sources and resistors can be modeled by a Thévenin equivalent consisting of a single voltage source in series with a single resistor. The Thévenin voltage is the open-circuit voltage of the original circuit, and the Thévenin resistance is the Thévenin voltage divided by the short-circuit current of the original circuit. Example 1 P104 Resistive model for CMOS LOW outputwith resistive load. Resistive model for CMOS HIGH outputwith resistive load. EXAMPLE 2 P107 3.5.3 Circuit Behavior with Nonideal Inputs P108 3.5.3 Circuit Behavior with Nonideal Inputs非理想输入时的电路特性 Example 3 P110 3.5.4 Fanout P111 3.5.4 Fanout （扇出） The fanout of a logic gate is the number of inputs that the gate can drive without exceeding its worst-case loading specifications. The fanout depends not only on the characteristics of the output, but also on the inputs that it is driving. Fanout must be examined for both possible output states, HIGH and LOW. 在不超出其最坏情况负载规格的条件下， 一个逻辑门能驱动的输入端个数。 扇出需考虑输出高电平和低电平两种状态 总扇出＝min（高态扇出，低态扇出） 直流扇出 和 交流扇出 EXAMPLE 3 P111 IImax for an HC-series CMOS input in any state is ±1 μA . The LOW-state fanout for an HC-series output driving HC-series inputs is 20. EXAMPLE 4 3.5.5 Effects of Loading 负载效应 输出负载大于它的扇出能力时（P111） In the LOW state, the output voltage VOL may increase beyond VOLmax. In the HIGH state, the output voltage VOH may fall below VOHmin.输出电压变差 Propagation delay to the output may increase beyond s